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Showing posts from February 10, 2019

Linux Kernel Boot Process in RISC V - SiFive Boards -Introduction

Linux Boot Process in RISC V SiFive boards using BBL  1. RISC V Boards are having 4 (Four) Modes.

     User mode -- User space programs runs
     Supervisor mode -- Kernel runs here
     Hypervisor mode -- Unspecified
     Machine mode --  Machine instructions
SBI (Supervisory Binary Interface) is interaction between Machine Mode & Supervisor Mode
it provide set of api for Supervisor to interact with Machine mode , like set_timer, system_shutdown, system_reset etc. 
2. In ARM CPU No.s & same is represented in RISC V as Hart Ids.
Boot CPU, or Hartid 0 is given to BBL for Initial boot process,
other HartIds are keep spining still HartId reaches to kernel init process.
3.The mhartidCSR is read,  so Linux can be passed a unique per-hart identifier.4. A PMP is set up to allow supervisor mode to access all of memory.5. Machine mode trap handlers, including a machine mode stack, is set up. bbl's machine mode code needs to handle both unimplemented instructions and machine-mode interrupts…