Skip to main content

First Stage Boot Loader (FSBL) for Zynq Zc702 using ZMD (Xilinx Microprocessor Debugger)

FSBL for Zynq ZC 702 Boards using xilinx XMD

This caputres or Identifies starting from Silicon version, intilization of CPU Regs. and Cache Intilization, set of basic controllers for First stage boot loading.

Thanks & Regards
Satiish G


Popular posts from this blog

DMA Debug - Zynq ZC702 - XMD Debugger

DMA Debug in Baremetal using XMD

Writing Startup Code for ARM Cortex M4 Controllers

STM32F4 Board bringup using OpenOCD

1.STM32F4 uses ARM Cortex M4 Controller
2.Internal Jtag pin present on the STM32F4 board supports for Debugging kernel which is already flashed on the Board.
3.STM32F4 using RIOT (Revoultionay IOT ) Micro Kernel.

Adding screenshots in sequence from Reset vector table.


Steps followed for writing startup code:
1.Initialize vector table
          2. Enter  to reset_vector()
         3. Copy .data section to RAM
         4. Initialize BSS section to Zeros
         5. Call board_init () 
               (call peripherals _init & cpu_init)
         6. Call libc_init_array()
         7. Call kernel_init()

Writing Startup Code for ARM Cortex A9 - Board bringup series - ZED Board

ZED Board uses Dual ARM Cortex A9
ZED board internally presents Debugger called XMD (Xilinx Microprocessor Debugger)
Xilinx provides Xilinx - SDK which supports Bare metal driver debug using XMD (XMD is having Node locked License)

This boot process is equal to debug using Hardware debugger like Lauterbach /ARM DS-5 /Segger Debugger & the Same is not possible with KGDB.
KGDB is supported grom GNU tools which can enter the Code in RAM (Maxium 4 Stack frames), Debugging code present outside the RAM is possible through Physical debuggers only.

Cortex A9 Processor boot method in Zynq SoC:

   1. The boot.S file contains a minimal set of code for transferring control from the processor's reset      2. Location to the start of the application. It performs the following tasks.
       Invalidate L1 caches, TLBs, Branch Predictor Array, etc.
       Invalidate L2 caches and initialize L2 Cache Controller.
      Enable caches and MMU
     Load MMU translation table base address into TLB  …