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DMA Debug - Zynq ZC702 - XMD Debugger

DMA Debug in Baremetal using XMD


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Linux Kernel Boot Process in RISC V - SiFive Boards -Introduction

Linux Boot Process in RISC V SiFive boards using BBL  1. RISC V Boards are having 4 (Four) Modes.

     User mode -- User space programs runs
     Supervisor mode -- Kernel runs here
     Hypervisor mode -- Unspecified
     Machine mode --  Machine instructions
SBI (Supervisory Binary Interface) is interaction between Machine Mode & Supervisor Mode
it provide set of api for Supervisor to interact with Machine mode , like set_timer, system_shutdown, system_reset etc. 
2. In ARM CPU No.s & same is represented in RISC V as Hart Ids.
Boot CPU, or Hartid 0 is given to BBL for Initial boot process,
other HartIds are keep spining still HartId reaches to kernel init process.
3.The mhartidCSR is read,  so Linux can be passed a unique per-hart identifier.4. A PMP is set up to allow supervisor mode to access all of memory.5. Machine mode trap handlers, including a machine mode stack, is set up. bbl's machine mode code needs to handle both unimplemented instructions and machine-mode interrupts…

Writing Startup Code for ARM Cortex A9 - Board bringup series - ZED Board

ZED Board uses Dual ARM Cortex A9
ZED board internally presents Debugger called XMD (Xilinx Microprocessor Debugger)
Xilinx provides Xilinx - SDK which supports Bare metal driver debug using XMD (XMD is having Node locked License)

This boot process is equal to debug using Hardware debugger like Lauterbach /ARM DS-5 /Segger Debugger & the Same is not possible with KGDB.
KGDB is supported grom GNU tools which can enter the Code in RAM (Maxium 4 Stack frames), Debugging code present outside the RAM is possible through Physical debuggers only.

Cortex A9 Processor boot method in Zynq SoC:

   1. The boot.S file contains a minimal set of code for transferring control from the processor's reset      2. Location to the start of the application. It performs the following tasks.
       Invalidate L1 caches, TLBs, Branch Predictor Array, etc.
       Invalidate L2 caches and initialize L2 Cache Controller.
      Enable caches and MMU
     Load MMU translation table base address into TLB  …